1. Technical Field
The disclosure relates to a semiconductor substrate assembly.
2. Related Art
To fulfill the high density package and to improve the channel bandwidth of the high speed integrated circuit system, a through-silicon via (TSV) is a key point in the three dimension integrated circuit (3D ICs) technique. In the integrated circuit technique of the 3D ICs, the TSV package technique is a main central technique and is available to connect a chip to one another vertically. This may reduce the length of connection lines greatly. Moreover, a silicon semiconductor interposer technique is also required in the outside connection of the 3D ICs, provides two dimension connection line layers, and provides three dimension connection lines among a plurality of laminated chips. For a high speed digital device implementing the 3D ICs, the TSVs and the semiconductor interposers are required to provide a wider bandwidth and to be small, and whereby the high speed digital device may have a high performance and a minimized size.
The TSV is insulated from the silicon substrate by a dielectric layer. This dielectric layer and the body of the semiconductor chip may cause a capacitance effect without ignoring therebetween according to the electric conductivity of the body. The capacitance effect and the silicon carrier with normal wear and tear may cause the distortion of high speed signal according to the variation of the frequency of the signal. To improve that signals in the high speed signal channel decay with the variation of the frequency thereof, the equalization circuit is implemented to reduce the transmission loss.
The present 3D IC technique may face non-linear signal transmission loss caused by the TSV, when transmitting signal through the TSV formed in the chip. The non-linear signal transmission loss may cause the signal distortion in high speed signal transmission, e.g. 20 Gbps or 25 Gbps. It may reduce the signal distortion to use the equalization circuit which provides a frequency response to transmission lines.
Generally, the passive equalization circuit requires resistance elements and capacitance elements. Such resistance elements and capacitance elements are belonged to additional materials and additional fabrication process in the design and manufacture of the chip, and this may cause the additional circuit design, fabrication process and area of the chip. Moreover, the equalization circuit of the silicon chip may occupy the more area of the chip and thereby increasing the costs and the design difficulty.